Self-assembled networks with neural computing attributes

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Self-assembled networks with neural computing attributes
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  Electrical Engineering, Department of  P. F. (Paul Frazer) Williams Publications  University of Nebraska - Lincoln  Year    Self-assembled networks with neuralcomputing attributes S. Bandyopadhyay ∗ L. Menon † N. Kouklin ‡ P. F. Williams ∗∗ Natale J. Ianno †† ∗ Virginia Commonwealth University, Richmond, VA † University of Nebraska - Lincoln ‡ Virginia Commonwealth University, Richmond, VA ∗∗ University of Nebraska - Lincoln, †† University of Nebraska - Lincoln, nianno1@unl.eduThis paper is posted at DigitalCommons@University of Nebraska - Lincoln.  1. Introduction The drive to nd alternative paradigms for computation, distinct from current silicon CMOS-based circuits, is fueled  by a belief in the device research community that the sil-icon MOSFET will ultimately run up against insurmount-able barriers. These barriers could be associated with ex-cessive power dissipation, breakdown of scaling laws, and certain fundamental limits imposed by the laws of quan-tum mechanics. While the fundamental limits are still a moot issue, excessive power dissipation is universally ac-knowledged to be a serious problem. The Semiconductor Industry Association’s National Technology Roadmap proj-ects that by the year 2007, the dynamic power dissipated in CMOS devices will be 600 nW / logic gate with a gate den-sity of 5 × 10 7 cm −2  , corresponding to a dissipation of 30 W cm −2 of chip area [1]. This gure is not signicantly beer than today’s gure, indicating that there is small chance of improvement in the future. As we make devices more en-ergy ecient, we also keep on adding more devices per unit area so the dissipation per unit area remains approx-imately constant. Present day personal computers consume less than 100 W, but this consumption can actually increase in future as clock speed goes up and the memory size increases. The to-tal power consumed by PCs in the US today is about 5% of the total national power generation [2]. Even if future computers do not consume any more power than they do at present, the number of computers in use will probably grow exponentially with time. At the same time, the lim-ited amount of natural fuel reserve, the enormous cost of  building a new power plant, the public suspicion of ssion energy, and cold fusion being in cold storage (perhaps per-manently) mean that power generation is not likely to in-crease even linearly with time, let alone exponentially. It is therefore likely that computers will soon begin to consume a signicant fraction of the national power generation lead-ing to a drain on the energy supply. Therefore, making computing devices more energy ecient (less dissipative) is a primary concern. In a seminal paper published in 1961 [4], Rolf Lan-dauer addressed the fundamental issue of dissipation and showed that the minimum energy that must be dissi-pated in a single logicall y irreversibl e bit operation is k T ln 2 which is about 4 × 10 −21  J at room temperature. This g-ure is far smaller than what CMOS or single-electron tran-sistors [5] will dissipate in a logic bit operation by the year 2007, but the very existence of this gure portends a fun-damental limit. Assuming that the most advanced devices, constrained only by the Landauer limit, will switch in 1 ps, the power dissipated will be 4 nW / gate. Moreover, assum-ing that heat sinking technology will allow removal of only Published in Smart Materials and Structures   11 (2002), pp. 761–766. Copyright © 2002 IOP Publishing Ltd. Used by permission.   hp://   Submied July 17, 2002; revised August 2, 2002; published online September 20, 2002. Self-assembled networks with neural computing aributes S. Bandyopadhyay 1  , L. Menon 2  , N. Kouklin 2  , P. F. Williams 2  , and N. J. Ianno 2 1 Department of Electrical Engineering, Virginia Commonwealth University, Richmond, VA 23284, USA 2 Department of Electrical Engineering, University of Nebraska–Lincoln, Lincoln, NE 68588-0511, USA Corresponding author  — S. Bandyopadhyay, Email:   Abstract Two-dimensional arrays of vertical quantum wire Esaki tunnel diodes, laterally connected to their nearest neighbors by resistive/capacitive connections, constitute a powerful and versatile neu-romorphic architecture that can function as classical Boolean logic circuits, associative memory, image processors, and combinatorial optimizers. In this paper, we discuss the basic philosophy  behind adopting this architecture for nanoelectronic circuits and report on our experimental prog-ress towards synthesizing this system. 761  762 S. B  .   S M  S   11 (2002)   1–10 kW cm −2 [3], the gate density will saturate to 2.5 × 10 13 gates cm −2 unless dramatic improvements in heat sinking are achieved. The alternative is to seek ways to circumvent the k T ln 2 barrier. Fortunately, Landauer [4] also showed that k T ln 2 is not an absolute, fundamental limit. Energy dissipation accrues from physical irreversibility which comes about because of logical irreversibility. If a bit operation can be carried out in a logically reversible manner, then the energy dissipa-tion can, in principle, approach zero. Concrete proposals for such “dissipationless” systems were advanced by Ben-ne [6, 7], Tooli [8], Fredkin and Tooli [9], Likharev [10], and Landauer [11] among others. None of these proposals envisioned nanoelectronic implementation. Recently, some nanoelectronic versions have appeared in the literature [12–15].Ultimately, the burgeoning eld of quantum   comput-er s may lead to completely dissipationless computing ma-chinery capable of solving classically intractable problems [16, 17]. While considerable progress is being made in these directions, the eld is also beset with diculties accruing mostly from materials and device shortcomings. Quantum computers and dissipationless devices are fu-turistic constructs. Although they have been demonstrated in superconducting systems, nuclear magnetic resonance devices, ion traps, etc, nanoscale compact solid-state sys-tems have remained elusive. On the other hand, rapid ad-vances are being made in nanoelectronics where there may  be immediate opportunities for signicant progress in the short term. In particular, there are unexplored vistas in un-conventional architectures where nanoelectronics may pro-vide a breakthrough within the next few years. 2. Nanoelectroni c architecture s In classical electronic devices (e.g. MOSFETs, bipolar junc-tion transistors), switching is basically accomplished by moving charges from one region of space to another. In the case of MOSFETs, charge is moved from the source contact into the channel region under the action of a gate poten-tial to switch the transistor “on.” To switch the transistor “o,” charge is moved from the channel into the drain by a change of the gate potential. It takes energy to move charge around and this energy is ultimately dissipated as heat. The smaller the amount of charge that one has to move (in switching a device on or o), the less the dissipation. Roughly speaking, the amount of charge Δ Q  involved in switching a device using a voltage swing Δ V   is given by Δ Q = C Δ V (1)   where C  is the capacitance associated with the control ter-minal, namely the terminal where the voltage swing ΔV is applied (the “gate” in the case of a MOSFET). The amount of energy dissipated in switching this device is roughly C( Δ V) 2 . It is therefore obvious that decreasing the capaci-tance C  reduces dissipation. Since C  is related to the area of the device, a small area helps. A good example of a device where this precept is exploited directly is the single-elec-tron transistor that has a very small capacitance and conse-quently, very lile power dissipation [18]. Smaller size promises reduced power dissipation  pe r de-vice . This motivates downscaling of device size. Another mo-tivating factor is the need for faster speed and higher clock frequency. The switching time is basically the time it takes to move charges from one region of space to another, namely the so-called transit time. This time is essentially L/v sat  where L  is the distance over which charge has to be moved (the “channel length” in the case of a MOSFET) and v sat  is the sat-urated velocity of the charge carriers. Obviously, the shorter the length L  , the smaller the switching time and the faster the switching speed. Therefore, “small” also means “fast.” The association of increased speed and reduced power dissipation (both highly desirable traits) with “smallness” has gradually evolved “microelectronics” to “nanoelectron-ics.” Industry fabrication lines are at present pursuing 90 nm feature sizes, and oating gate transistors with feature sizes of 10 nm have been demonstrated [19]. 2.1. Shortcomings of nanoelectronic devices While nanometer-sized devices are fast and energy ecient, they also have a few shortcomings. First, the small size of the device makes it dicult to aach very many leads to it. Therefore, random wired architectures, that are used in conventional logic and memory circuits, are inappropriate for nanoelectronics. Second, the small size also precludes large voltage or current swings. Hence the ability to drive several successive stages suers. Third, the fan-in/fan-out of a nanometer-sized device is small. Take the ultimate case of a device which outputs a single electron charge under a voltage swing. Since the electron cannot be split into halves (or smaller fractions), this device can, at best, drive only one succeeding device. Finally, nanoelectronic devices typi-cally do not have much power gain. Therefore, they are not exactly tailor-made for logic circuits since logic devices re-quire power gain to restore signal levels at logic nodes [20]. It therefore behooves us to look for alternate architec-tures, very dierent from today’s Boolean logic-based circuit paradigms, to exploit the full power of nanoelectronics. 2.2. Locally interconnected architectures and edge-driven  paradigms In a series of papers, a group of researchers from Texas In-struments [21] introduced a concept that is suitable for na-noelectronics. This was a generic concept with no particu-lar implementation. The idea had three ingredients: (i) Every device is connected only to its nearest neighbors (no long-range wiring). Thus, each device has only a few connections. These connections could be of a quan-tum mechanical nature (such as tunneling) instead of a physical wire. (ii) All input data are provided to devices on the periphery of the chip. Interior devices are never accessed from external leads since the packing density in the interior of the chip is very dense. All exterior leads access only the peripheral devices. (iii) The inputs provided to the peripheral devices are com-municated to the interior devices via the connections  between the peripheral and interior devices. The in-terior devices then perform the signal processing or  S-      763 computation in response to the input and convey the results to other peripheral devices which act as output ports. The external leads connect to these output ports to access the results. This scheme is pictorially depicted in gure 1. This architecture is synergistic with nano-electronic devices. 2.3. A neuromorphic implementation Our past work has involved a specic implementation of a locally interconnected edge-driven architecture that per-forms neuromorphic functions. It can be adapted to Bool-ean logic as well. Most importantly, it was inspired by re-cent advances in chemical self-assembly and is therefore synergistic with an inexpensive and versatile production method. This architecture, exhibiting the aributes of univer-sal computing machinery, was proposed by Roychowd-hury et al.  [22–25]. The basic system is shown in gure 2. It consists of a two-dimensional periodic array of nanome-ter-sized metallic islands with nearest-neighbor electrical interconnections, self-assembled on a substrate whose cur-rent–voltage characteristic has a non-monotonic  non-linear-ity. The simplest choice for the substrate is a resonant tun-neling diode (RTD). Other choices, such as an Esaki tunnel diode, are also possible and may be preferable for silicon- based implementations. The system in gure 2(a) can realize logic circuits, as-sociative memory, signal processors, and combinatorial op-timizers which solve such problems as the traveling sales-man problem by mapping it onto the charging dynamics of the network. The details have been given in a number of publications such as [22–26]. The reader is referred to these references for more detail. In particular, the last ar-ticle is a review article summarizing the salient features of this paradigm. 3. Self-assembled networks for computing architectures In this paper, we will not repeat the theoretical foundations of the architecture which have been dealt with in detail in the above-cited references. Instead, we will focus on exper-imental progress towards implementing the critical compo-nents of the circuitry. The architecture in question has been developed with the generic features of self-assembly synthesis in mind. We designed the system such that it must not only be compat-ible but also synergistic with self-assembly. Our own expe-rience with self-assembly gives us enough reasons to adopt this philosophy. Traditionally, nanoscale paerns have been delineated  by direct-write ne-line lithography. Direct writing of highly complex and dense integrated circuits is extremely time consuming and can run into several hours. This, cou-pled with the fact that direct writing is a serial  technique whereby each wafer is paerned one at a time,  can lead to an unacceptably slow throughput. Chemical self-assembly techniques, on the other hand, are  parallel  in nature, i.e. several wafers can be processed si-multaneously. They are well suited for realizing highly uni-form sheets of organized nanostructures, e.g. molecules on surfaces (self-assembled monolayers or SAMs), clusters/nanoparticles/wires of controlled dimensions at the nanome-ter scale, and uniform two-dimensional and/or three-dimen-sional arrays of structures such as clusters, islands, lines, and nanopores on surfaces. These techniques are useful for de-ning various nanometer-scale ultradense arrays with rela-tively low cost and high throughput. Of course, uniform ar-rays by themselves are usually not sucient for realizing useful computational or signal processing circuits. It is likely that some form of lithography, at a scale larger than the min-imum element size, will be required in order to connect and isolate blocks of devices. This is not a serious drawback since the nest features will still be produced by self-assembly. A key component required to realize circuits of the type shown in gure 2 is the formation of ordered metallic dot arrays on a substrate. Each dot must be coupled to the sub-strate via a non-linear conductor exhibiting a non-mono-tonic current–voltage characteristic. The non-linear element of choice is an Esaki tunnel diode that exhibits a negative dierential resistance. Thus, each dot must be used as an etch mask to electrically isolate a columnar Esaki diode structure underneath. Finally, nearest-neighbor electrical connections must be established between these dots. Self-assembly synthesis techniques can provide highly or-dered arrays of metallic islands at the nanometer scale on ar- bitrary substrates. These islands can be used as a natural mask to mesa-isolate structures with desired transport characteris-tics in the underlying substrate. Finally, a resistive lm can be evaporated on the surface to complete electrical connections  between nearest-neighbor dots. This is the most straightfor-ward, but perhaps not the most elegant, approach. 4. Self-assembled template-based synthesis In this section, we describe our simple approach to self-as-sembling ordered arrays of nanometer-sized dots on a p + – Figure 1.  A generic locally interconnected architecture employing the edge-driven paradigm.  764 S. B  .   S M  S   11 (2002)   n + wafer that acts as an Esaki tunnel diode structure. This is the most critical step in the realization of the neuromorphic architecture. Anodic alumina lms containing ordered arrays of nanopores are widely used for self-assembling semicon-ductor quantum dots and wires of uniform diameter. We will adapt that technique to create a regimented array of metal nanodots on a p + –n + wafer. Electrochemical self-assembly of the anodic alumina lm consists of the following steps. A 99.999% pure 100 µ m aluminum foil is rst degreased in trichloro-ethylene, washed in distilled water, and electropolished at 30 V for 60 s in LECO-1 solution consisting of perchloric acid, ethanol,  butyl cellusolve, and water. The foil is then  anodized in either sulfuric or oxalic acid at room temperature using a current density of 25 mA cm −2 . This results in the formation of a porous alumina lm on the surface with a pore diame-ter of about 8 nm and an areal pore density of ~10 11 cm −2 for sulfuric acid anodization. For oxalic acid anodization, the pore diameter is 50 nm and the pore density is ~10 10 cm −2 . An atomic force micrograph of a porous lm produced by anodization in oxalic acid is shown in gure 3. The porous lm can be used to create an ordered ar-ray of metallic nanodots following a technique proposed  by Masuda and Satoh [27]. The porous lm is coated on the surface with an organic binder (which provides mechan-ical support during later processing steps). Next, the alu-minum backing is dissolved in HgCl 2 . Then, the alumina  barrier layer is removed from the boom of the lm (for a denition of “barrier layer,” see gure 4) by etching in phosphoric acid at 100 °C. Thereaer, the organic binder is dissolved in acetone to create an ultrathin alumina lm with “see-through” pores that oats up to the surface of the acetone. This ultrathin lm is then captured on a silicon p + –n + substrate. Finally, gold is evaporated on the surface using e-beam evaporation. The Au atoms travel through the pore openings and lodge themselves on the surface of the silicon wafer. The alumina template is then removed in phosphoric acid, leaving behind a regimented array of gold nanodots on the surface. These steps are shown in g-ure 4. An atomic force micrograph of 50 nm diameter Au nanodots produced by this technique is shown in gure 5. The next step in the process is to use the Au dots as an etch mask to reactive-ion-etch mesas into the underlying Figur e 2 . A generic array of metallic islands deposited on a p + –n + structure that acts as a vertical Esaki tunneling diode. Although not shown ex-plicitly in this gure (for the sake of clarity), it is understood that each island caps a mesa-isolated Esaki tunneling diode underneath. These mesas are dened by reactive ion etching using the metal islands themselves as masks. Each island is connected only to its nearest neighbor by resistive/capacitive links (these links can be realized simply by lateral tunneling between nearest-neighbor nodes; since tunneling current falls o exponen-tially with distance, tunneling links can always be viewed as “nearest-neighbor” couplings). A subset of the islands serve as program nodes which are driven by external current sources. Another subset of islands serve as input/output ports, and the remaining islands introduce complexity to the system through non-linear conductive links to the substrate. Figure 3.  An atomic force micrograph of a porous alumina lm pro-duced by anodization of aluminum in oxalic acid. The dark areas are the pores and the surrounding white areas are alumina. The average pore diameter is 50 nm.
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