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This paper describes the design of a high-speed CMOSTrack/Hold circuit in front of an ADC. The Track/Hold circuit employsdifferential open-loop architecture, very linear source follower inputbuffers, NMOS sampling switches and bootstrap

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Analog Integrated Circuits and Signal Processing, 27, 161–170, 2001
C
2001 Kluwer Academic Publishers. Manufactured in The Netherlands.
High-Speed CMOS Track/Hold Circuit Design
∗
HARUO KOBAYASHI,
1,
†
MOHD ASMAWI MOHAMED ZIN,
1
KAZUYA KOBAYASHI,
1
HAO SAN,
1
HIROYUKI SATO,
1
JUN-ICHI ICHIMURA,
1
YOSHITAKA ONAYA,
1
NAOKI KUROSAWA,
1
YASUYUKI KIMURA,
2
YASUSHI YUMINAKA,
1
KOUJI TANAKA,
2
TAKAO MYONO
2
AND FUMINORI ABE
2
1
Department of Electronic Engineering, Gunma University, 1-3-1 Tenjin-cho Kiryu 376-8515 Japan
2
Semiconductor Company, Sanyo Electric Corp., 1-1-1 Sakata Oizumi-Machi Ora-Gun Gunma 370-0596 Japan E-mail: k haruo@el.gunma-u.ac.jp
Received December 20, 1999; Revised June 20, 2000; Accepted June 28, 2000
Abstract.
This paper describes the design of a high-speed CMOS Track/Hold circuit in front of an ADC. TheTrack/Hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOSsampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply volt-age. SPICE simulations with MOSIS 0.35
µ
m CMOS BSIM3v3 parameters showed that it achieves a signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mWpower consumption.
Key Words:
Track/Hold circuit, Sample/Hold circuit, AD converter, sampling, CMOS
I. Introduction
Digital signal processing (DSP) is becoming popu-lar and the ADC is an essential component for DSPbecause most signals in the natural world—such asvoltage, current, and voice—are analog. Hence higherperformance ADCs are in demand. Although somehigh-speed ADC architectures (such as ﬂash and fold-ing/interpolation) do not require Track/Hold (T/H) cir-cuits
in principle
[1],
in practice
they are required infront of high speed ADCs to improve their AC perfor-mance. Also CMOS implementation is very important—because of its low cost, and because single-chip in-tegration of analog and digital parts is possible. Weare designing a high-speed 8-bit CMOS ADC system(which may be reported elsewhere), and in this paperwe report the design of a high-speed CMOS T/H cir-cuit for this ADC system. Most CMOS T/H circuitswhose accuracy is better than 8 bits employ a closed-loop architecture. However a closed-loop conﬁgura-tion is inherently slower than open loop. High-speedhigh-precision open-loop T/H circuits for low voltage
†
Corresponding author.
∗
Note: A part of the content was presented at ICECS’99 (W4B2: AHigh-Speed CMOS Track/Hold Circuit).
operation have already been implemented with BiC-MOS and bipolar technologies [2,3]. We investigateda new open-loop CMOS circuit topology which givesfaster operation while maintaining an accuracy of bet-ter than 8 bits. Also circuit design with a power supplyof 3.3 V (or less) was mandated because a 0
.
35
µ
mCMOS process was used.
II. Circuit Design
We designed a high-speed T/H circuit (200 MS/s,8-bitaccuracyupto100MHzinput)usingMOSIS0.35
µ
mCMOSprocess(single-poly,n-well)BSIM3v3pa-rameters with 3.3 V supply voltage, and details are asfollows:
A. Open-Loop Architecture
T/H circuit architecture can be classiﬁed into twoclasses (Fig. 1):
open-loop
and
closed-loop
[1,4]. Theopen-loop T/H circuit is suitable for high speed butnot for high precision, while a closed-loop circuit issuitable for high precision but not for high speed. MostCMOS T/H circuits proposed/implemented so faremploy a closed-loop architecture to obtain better than
162
Kobayashi et al.
(a)(b)
Fig. 1.
T/H circuit architectures. (a) Open-loop architecture. (b)Closed-loop architecture.
8-bit accuracy; for CMOS implementation, the non-linearity of input/output buffers and nonlinear chargeinjection of sampling MOS switches have limited theaccuracyoftheopen-looparchitectureto6bits[1].Re-cently a high-speed, high-precision open-loop CMOST/Hcircuitwasreported[6],butthisseemstobeanex-ceptional case. In this paper we employ an open-looparchitecture to achieve high speed (200 MS/s), but adifferent circuit topology from [6] was used to achievebetter than 8-bit accuracy.
B. Input Buffer
RecentlyHadidietal.[5]proposedaverylinearsourcefollower buffer for 3.3 V operation (Fig. 2), withthe current source implemented by a single MOSdevice with
L
1
=
L
2
and
W
1
=
W
2
(instead of a cas-code current source) and the output of
V
out
operatedaround
V
dd
/
2 (
V
dd
: power supply voltage). We employthis circuit as an input buffer, and its simulated DC lin-earityisbetterthan11bits,asshowninthenextsection.Note that the sizes of the two buffers are different inFig. 5(a); one is
W
=
200
µ
m (
L
=
0
.
35
µ
m), and theother is
W
=
50
µ
m (
L
=
0
.
35
µ
m). Scaling the sizeof the buffer (which drives
C
B
) to
W
=
50
µ
m is done
Fig.2.
Averylinearsourcefollowerbuffer[6].AsingleMOSdevicecurrent source with
L
1
=
L
2
,
W
1
=
W
2
is used instead of a cascadecurrent source.
to save power, but note that
V
gs
of both buffers are thesamebecausetheirsizesandbiascurrentsarescaledbythesamefactor(i.e.,theirinputPMOSsizesandcurrentsource PMOS sizes are scaled by the same factor).
C. MOS Switch and Bootstrap Switch Driver Circuit
Two problems in using an NMOS sampling switch(Fig. 3) in a T/H circuit are:
input-dependent, ﬁniteON-resistance
and
input-dependent charge injection
.
•
Input-dependent, ﬁnite ON-resistance of MOS sam- pling switch:
For a square-law NMOS device that
Fig. 3.
Sampling circuit with an NMOS switch.
High-Speed CMOS Track 163
operates in the triode region, its ON-resistance
R
on
is given by
R
on
=
1
µ
n
C
oxW L
(
V
gs
−
V
th
)
(1)where
µ
n
is the electron mobility,
W
is the channelwidth,
L
is the channel length,
C
ox
is the gate ox-ide capacitance per unit area,
V
gs
is the gate-sourcevoltage and
V
th
is the threshold voltage. Since
V
gs
is equal to
V
dd
−
V
in
in Fig. 3,
R
on
depends on
V
in
,whichcausesharmonicdistortion[4].Alsosince
V
dd
is relatively small (3.3 V),
V
gs
is small, and hence inorder to make
R
on
sufﬁciently small for widebandtrack mode,
W
has to be large; however this causeslarge charge injection as described below.
•
Input-dependent charge injection:
When a MOSswitch turns off, the amount of charge
Q
ch
injectedto its channel is given as follows [1]:
Q
ch
≈
WLC
ox
(
V
gs
−
V
th
).
(2)We see that since
V
gs
is equal to
V
dd
−
V
in
in the T/Hcircuit,
Q
ch
depends on
V
in
which causes pedestalerrors to the T/H circuit [1].NotethataCMOSswitchwithadummyswitchinsteadof an NMOS switch has also problems as a samplingswitch [1]. We solve these two problems by adoptinga bootstrap switch driver circuit for an NMOS sam-pling switch and its operation principle is as follows(Fig. 4):
•
Inholdmode,acapacitorof
C
B
ischargedto
C
B
V
dd
,while the gate of the NMOS sampling switch is con-nected to ground to turn it off.
•
Intrackmode,oneterminalof
C
B
isconnectedto
V
in
through a buffer and the other terminal is connectedto the gate of the NMOS sampling switch. Since thevoltage between the terminals is
V
dd
, the gate volt-age is
V
dd
+
V
in
. The source voltage of the NMOSswitchis
V
in
andthen
V
gs
oftheNMOSswitchis
V
dd
,whichisindependentof
V
in
andlargerthan
V
dd
−
V
in
.Since
V
gs
of the sampling switch in track mode is
V
dd
,which is independent of
V
in
and larger than
V
dd
−
V
in
, this circuit solves the above two problems. Fig. 5shows the circuit implementation, and its features areas follows:
•
The switch
SW
1 is realized with an NMOS deviceinstead of a PMOS device; if it is realized with aPMOS device, it may not turn off even when its gatevoltage is
V
dd
because the voltage of node 1 can be
Fig. 4.
Proposed open-loop T/H circuit with a boot-strap switchdriver circuit.
higher than
V
dd
. Note that since the switch
SW
1 isrealized with an NMOS device, the control voltage(gate voltage) to turn on
SW
1 is 1
.
5
V
dd
produced bya 1
.
5
V
dd
generator as proposed in Fig. 6; if
V
dd
isused instead of 1
.
5
V
dd
to turn on
SW
1,
V
gs
of thesampling switch in track mode is equal to
V
dd
−
V
th
instead of
V
dd
.
•
The body of the PMOS switch
SW
2 is connected tonode 1.
Remark:
(i) In Fig. 5(a),
clk
is a 200 MHz samplingclock with 50% duty toggling between 0 and
V
dd
and
clk
is its inversion while
clk
′
toggles between
V
dd
and1
.
5
V
dd
(see Fig. 6).(ii) A similar bootstrap circuit topology is used in[7], and the main difference is that the proposed circuithere uses two input buffers (one for the signal path andthe other for sampling gate drive (see Fig. 4)) whilethe circuit in [7] uses only one buffer. Hence the lattercircuit has extra parasitic capacitances and may sufferfrom clock kickback noise in the signal path, whilethe proposed circuit needs more power due to the extrabuffer;themainadvantagesoftheproposedcircuitherewould be better accuracy and higher speed, while itsdisadvantage is larger power consumption.
164
Kobayashi et al.
(a)(b)(c)
Fig. 5.
Circuit implementation of the proposed open-loop T/H circuit. (a) Whole circuit diagram. Actual circuit is differential but shownsingle-ended for simplicity. (b) Track mode. (c) Hold mode.
High-Speed CMOS Track 165
(a) (b)(c)
Fig. 6.
Proposed 1
.
5
V
dd
generator circuit. (a) Circuit diagram. (b) Operation when
clk
=
0. (c) Operation when
clk
=
V
dd
.
(iii) The ﬁrst-order effects of the input-signal-dependency of the sampling switch ON-resistance andcharge injection are canceled by the proposed method,however, the second-order effects remain; the body of the sampling switch is connected to
V
ss
due to theN-well process and hence
V
bs
changes according to theinputsignallevel
V
in
(
t
)
.Sincethethresholdvoltage
V
th
varies by
V
bs
(body effect) and also the mobility
µ
n
isa function of
V
bs
as well as
V
gs
(mobility degradation),
R
on
of equation (1) and
Q
ch
of equation (2) change ac-cording to
V
in
(
t
)
. The BSIM3v3 SPICE model whichwe have used incorporates all of these effects [14–16],andwehavefoundbySPICEsimulationwithBSIM3v3modelthatthedominantharmonicscausedbythebodyeffect and the mobility degradation are second order,and are cancelled by the differential topology; in thesingle-ended case, SNDR degradation due to the bodyeffect and the mobility degradation is about by 7 dB,while in the differential topology case it is about 2 dBfor
f
in
=
100 MHz,
f
s
=
200 MHz.(iv)
C
B
and associated parasitic capacitances maycause charge sharing problems [7]. However we use1 pF value of
C
B
which is fairly large amount com-pared to associated parasitic capacitances and hencethe voltage variation due to charge sharing is small.Further our simulation indicated that the voltage vari-ation across
C
B
is insensitive to overall T/H circuitperformance.
D. Hold Capacitor and Output Buffer
We consider that the T/H circuit uses the input capaci-tancesofafollowingADCasholdcapacitors(i.e.,therewill be no explicit hold capacitors in the layout whenthe T/H circuit is combined with an ADC) and also itdoes not need output buffers (Fig. 7); this topology cansave power and avoid the linearity degradation due tooutput buffers [8,9].
E. Sampling Clock Jitter
Aperture jitter effects are very serious for the high-speed T/H circuit, and its detailed analysis is describedin[11,12],whereSNRduetosamplingclockjitterwith
rms
valueof
ǫ
rms
forasinusoidalinputoffrequency
f
in

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